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TMS320F2811 数据表(PDF) 22 Page - Texas Instruments |
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TMS320F2811 数据表(HTML) 22 Page - Texas Instruments |
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22 / 173 page  Introduction 22 April 2001 − Revised July 2007 SPRS174O Table 2−2. Signal Descriptions† (Continued) NAME DESCRIPTION PU/PD§ I/O/Z‡ PIN NO. NAME DESCRIPTION PU/PD§ I/O/Z‡ 128-PINP BK 176-PINP GF 179-PING HH ADC ANALOG INPUT SIGNALS (CONTINUED) ADCINB7 F5 9 9 I ADCINB6 D1 8 8 I ADCINB5 D2 7 7 I 8-Channel Analog Inputs for Sample-and-Hold B. ADCINB4 D3 6 6 I 8-Channel Analog Inputs for Sample-and-Hold B. The ADC pins should not be driven before the ADCINB3 C1 5 5 I The ADC pins should not be driven before the VDDA1, VDDA2, and VDDAIO pins have been fully powered up. ADCINB2 B1 4 4 I VDDA1, VDDA2, and VDDAIO pins have been fully powered up. ADCINB1 C3 3 3 I ADCINB0 C2 2 2 I ADCREFP E2 11 11 I/O ADC Voltage Reference Output (2 V). Requires a low ESR (50 m Ω − 1.5 Ω) ceramic bypass capacitor of 10 µF to analog ground. (Can accept external reference input (2 V) if the software bit is enabled for this mode. 1−10 µF low ESR capacitor can be used in the external reference mode.) ADCREFM E4 10 10 I/O ADC Voltage Reference Output (1 V). Requires a low ESR (50 m Ω − 1.5 Ω) ceramic bypass capacitor of 10 µF to analog ground. (Can accept external reference input (1 V) if the software bit is enabled for this mode. 1−10 µF low ESR capacitor can be used in the external reference mode.) ADCRESEXT F2 16 16 O ADC External Current Bias Resistor Use 24.9 k Ω ±5% for ADC clock range 1 − 18.75 MHz 20 k Ω ±5% for ADC clock range 18.75 MHz − 25 MHz ADCBGREFIN E6 164 116 Test Pin. Reserved for TI. Must be left unconnected. AVSSREFBG E3 12 12 ADC Analog GND AVDDREFBG E1 13 13 ADC Analog Power (3.3-V) ADCLO B3 175 127 Common Low Side Analog Input. Connect to analog ground. VSSA1 F3 15 15 ADC Analog GND VSSA2 C5 165 117 ADC Analog GND VDDA1 F4 14 14 ADC Analog 3.3-V Supply VDDA2 A5 166 118 ADC Analog 3.3-V Supply VSS1 C6 163 115 ADC Digital GND VDD1 A6 162 114 ADC Digital 1.8-V (or 1.9-V) Supply VDDAIO B2 1 1 3.3-V Analog I/O Power Pin VSSAIO A2 176 128 Analog I/O Ground Pin † Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA. ‡ I = Input, O = Output, Z = High impedance § PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3. The pullups/pulldowns are enabled in boundary scan mode. |
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