TMS320F2811 datasheet(57/173 Pages) TI

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Peripherals

April 2001 − Revised July 2007

SPRS174O

Peripherals

The integrated peripherals of the F281x and C281x are described in the following subsections:

•

Three 32-bit CPU-Timers

•

Two event-manager modules (EVA, EVB)

•

Enhanced analog-to-digital converter (ADC) module

•

Enhanced controller area network (eCAN) module

•

Multichannel buffered serial port (McBSP) module

•

Serial communications interface modules (SCI-A, SCI-B)

•

Serial peripheral interface (SPI) module

•

Digital I/O and shared pin functions

4.1

32-Bit CPU-Timers 0/1/2

There are three 32-bit CPU-timers on the F281x and C281x devices (CPU-TIMER0/1/2).

Timer 2 is reserved for DSP/BIOS. CPU-Timer 0 and CPU-Timer 1 can be used in user applications. These

timers are different from the general-purpose (GP) timers that are present in the Event Manager modules

(EVA, EVB).

NOTE: If the application is not using DSP/BIOS, then CPU-Timer 2 can be used in the

application.

Borrow

Reset

Timer Reload

SYSCLKOUT

TCR.4

(Timer Start Status)

TINT

16-Bit Timer Divide-Down

TDDRH:TDDR

32-Bit Timer Period

PRDH:PRD

32-Bit Counter

TIMH:TIM

16-Bit Prescale Counter

PSCH:PSC

Borrow

Figure 4−1. CPU-Timers

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