TMS320F2811 datasheet(98/173 Pages) TI

98 / 173 page

Electrical Specifications

April 2001 − Revised July 2007

SPRS174O

EMU0

EMU1

TMS

TDI

TDO

TCK

VDDIO

DSP

EMU0

EMU1

TMS

TDI

TDO

TCK

TCK_RET

6 inches or less

GND

JTAG Header

VDDIO

TRST

Figure 6−5. Emulator Connection Without Signal Buffering for the DSP

6.9

Power Sequencing Requirements

TMS320F2812/F2811/F2810 silicon requires dual voltages (1.8-V or 1.9-V and 3.3-V) to power up the CPU,

Flash, ROM, ADC, and the I/Os. To ensure the correct reset state for all modules during power up, there are

some requirements to be met while powering up/powering down the device. The current F2812 silicon

reference schematics (Spectrum Digital Incorporated eZdsp. board) suggests two options for the power

sequencing circuit.

Power sequencing is not needed for C281x devices. In other words, 3.3-V and 1.8-V (or 1.9-V) can ramp

together. C281x can also be used on boards that have F281x power sequencing implemented; however, if

the 1.8-V (or 1.9-V) rail lags the 3.3-V rail, the GPIO pins are undefined until the 1.8-V rail reaches at least

1 V.

•

Option 1:

In this approach, an external power sequencing circuit enables VDDIO first, then VDD and VDD1 (1.8 V or

1.9 V). After 1.8 V (or 1.9 V) ramps, the 3.3 V for Flash (VDD3VFL) and ADC (VDDA1/VDDA2/AVDDREFBG)

modules are ramped up. While option 1 is still valid, TI has simplified the requirement. Option 2 is the

recommended approach.

•

Option 2:

Enable power to all 3.3-V supply pins (VDDIO, VDD3VFL, VDDA1/VDDA2/VDDAIO/AVDDREFBG) and then

ramp 1.8 V (or 1.9 V) (VDD/VDD1) supply pins.

1.8 V or 1.9 V (VDD/VDD1) should not reach 0.3 V until VDDIO has reached 2.5 V. This ensures the reset

signal from the I/O pin has propagated through the I/O buffer to provide power-on reset to all the modules

inside the device. See Figure 6−11 for power-on reset timing.

•

Power-Down Sequencing:

During power-down, the device reset should be asserted low (8

µs, minimum) before the VDD supply

reaches 1.5 V. This will help to keep on-chip flash logic in reset prior to the VDDIO/VDD power supplies

ramping down. It is recommended that the device reset control from “Low-Dropout (LDO)” regulators or

voltage supervisors be used to meet this constraint. LDO regulators that facilitate power-sequencing (with

eZdsp is a trademark of Spectrum Digital Incorporated.

TMS320F2811 数据表(PDF) 98 Page - Texas Instruments

TMS320F2811 数据表(HTML) 98 Page - Texas Instruments

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