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TMS320F2811 数据表(PDF) 103 Page - Texas Instruments |
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TMS320F2811 数据表(HTML) 103 Page - Texas Instruments |
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103 / 173 page  Electrical Specifications 103 April 2001 − Revised July 2007 SPRS174O Table 6−5. XCLKIN Timing Requirements − PLL Bypassed or Enabled NO. MIN MAX UNIT C8 tc(CI) Cycle time, XCLKIN 6.67 250 ns C9 tf(CI) Fall time, XCLKIN 6 ns C9 tf(CI) Fall time, XCLKIN 6ns C10 tr(CI) Rise time, XCLKIN 6 ns C10 tr(CI) Rise time, XCLKIN 6 ns C11 tw(CIL) Pulse duration, X1/XCLKIN low as a percentage of tc(CI) 40 60 % C12 tw(CIH) Pulse duration, X1/XCLKIN high as a percentage of tc(CI) 40 60 % Table 6−6. XCLKIN Timing Requirements − PLL Disabled NO. MIN MAX UNIT C8 tc(CI) Cycle time, XCLKIN 6.67 250 ns C9 tf(CI) Fall time, XCLKIN Up to 30 MHz 6 ns C9 tf(CI) Fall time, XCLKIN 30 MHz to 150 MHz 2 ns C10 tr(CI) Rise time, XCLKIN Up to 30 MHz 6 ns C10 tr(CI) Rise time, XCLKIN 30 MHz to 150 MHz 2 ns C11 tw(CIL) Pulse duration, X1/XCLKIN low as a percentage of tc(CI) XCLKIN ≤ 120 MHz 40 60 % C11 tw(CIL) Pulse duration, X1/XCLKIN low as a percentage of tc(CI) 120 < XCLKIN ≤ 150 MHz 45 55 % C12 tw(CIH) Pulse duration, X1/XCLKIN high as a percentage of tc(CI) XCLKIN ≤ 120 MHz 40 60 % C12 tw(CIH) Pulse duration, X1/XCLKIN high as a percentage of tc(CI) 120 < XCLKIN ≤ 150 MHz 45 55 % Table 6−7. Possible PLL Configuration Modes PLL MODE REMARKS SYSCLKOUT PLL Disabled Invoked by tying XPLLDIS pin low upon reset. PLL block is completely disabled. Clock input to the CPU (CLKIN) is directly derived from the clock signal present at the X1/XCLKIN pin. XCLKIN PLL Bypassed Default PLL configuration upon power-up, if PLL is not disabled. The PLL itself is bypassed. However, the /2 module in the PLL block divides the clock input at the X1/XCLKIN pin by two before feeding it to the CPU. XCLKIN/2 PLL Enabled Achieved by writing a non-zero value “n” into PLLCR register. The /2 module in the PLL block now divides the output of the PLL by two before feeding it to the CPU. (XCLKIN * n) / 2 |
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