M32CSLASH8B datasheet(138/406 Pages) RENESAS

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M32C/8B Group

13. DMAC

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 121 of 385

A software trigger or an interrupt request generated by individual peripheral functions can be the DMA transfer request

source. Bits DSEL 4 to DSEL0 in the DMiSL register determine which source is selected. When a software trigger is

selected, a DMA transfer is started by setting the DSR bit in the DMiSL register to 1. When a peripheral function

interrupt request is selected, a DMA transfer is started by an interrupt request generation. The DMA transfer is

performed even if interrupts are disabled by the I flag, IPL, or Interrupt Control Register, since DMAC is free from

these affects. When an interrupt request (DMA request) is generated, the IR bit in the Interrupt Control Register

becomes 1. The IR bit, however, does not become 0 even if the DMA transfer is performed.

Table 13.1

DMAC Specifications

Item

Specification

Number of Channels

4 channels (cycle-steal method)

Transfer memory space

• From a given address in a 16-Mbyte space to a fixed address in a 16-Mbyte space

• From a fixed address in a 16-Mbyte space to a given address in a 16-Mbyte space

Maximum bytes transferred

128 Kbytes (when a 16-bit data is transferred)

64 Kbytes (when an 8-bit data is transferred)

DMA request source

• Falling edge or both edges of signals applied to pins INT0 to INT3

• Timer A0 to A4 interrupt requests

• Timer B0 to B5 interrupt requests

• UART0 to UART4 transmit/receive interrupt requests

• A/D0 interrupt request

• Software trigger

Channel priority

DMA0 > DMA1 > DMA2 > DMA3 (DMA0 has the highest priority)

Transfer unit

8 bits, 16 bits

Transfer address

Fixed address: one specified address

Incremented address: address which is incremented by a transfer unit on each

successive access.

(Source address and destination address cannot be both fixed nor both

incremented.)

Transfer

mode

Single transfer

Transfer is completed when the DCTi register (i = 0 to 3) becomes 0000h

Repeat transfer

When the DCTi register becomes 0000h, values of the DRCi register are reloaded

into the DCTi register and the DMA transfer continues.

DMA interrupt request

generation timing

When the DCTi register becomes from 0001h to 0000h, a DMA interrupt request is

generated.

DMA start

Single transfer

DMAC starts a data transfer when a DMA request is generated after bits MDi1 and

MDi0 in the DMDj register (j = 0 to 1) are set to 01b (single transfer), while the DCTi

Repeat transfer

DMAC starts a data transfer when a DMA request is generated after bits MDi1 and

MDi0 are set to 11b (repeat transfer), while the DCTi register is set to 0001h or higher

value.

DMA stop

Single transfer

• When bits MDi1 and MDi0 are set to 00b (DMA disabled)

• When the DCTi register becomes 0000h (no DMA transfer) at completion of DMA

transfer, or is set to 0000h by a program.

Repeat transfer

• When bits MDi1 and MDi0 are set to 00b (DMA disabled)

• When the DCTi register becomes 0000h (no DMA transfer) at completion of DMA

transfer, or is set to 0000h by a program while the DRCi register is 0000h.

Reload timing to registers DCTi

and DMAi

Values are reloaded when the DCTi register becomes from 0001h to 0000h in repeat

transfer mode.

DMA transfer time

Between SFR area and internal RAM transfer: minimum 3 bus clock cycles

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