M32CSLASH8B datasheet(142/406 Pages) RENESAS

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Under development

M32C/8B Group

13. DMAC

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 125 of 385

Figure 13.4

DRA0 to DRA3 Registers, DCT0 to DCT3 Registers, DRC0 to DRC3 Registers

b23

Symbol

DRA0

DRA1

DRA2 (SVP)(2)

DRA3 (VCT)(3)

Address

(CPU internal register)

After Reset

XXXXXXh

Function

DMAi Memory Address Reload Register(1) (i = 0 to 3)

Set an incremented source address or incremented destination

address

NOTES:

1. Use the LDC instruction to set registers DRA0 to DRA3.

2. To set the DRA2 register, write to the SVP register.

3. To set the DRA3 register, write to the VCT register.

Setting Range

000000h to FFFFFFh

(16 Mbytes)

b16 b15

b8 b7

Symbol

DCT0(2)

DCT1(2)

DCT2 (bank1:R0)(3)

DCT3 (bank1:R1)(4)

Address

(CPU internal register)

After Reset

XXXXh

0000h

Function

DMAi Transfer Count Register (i = 0 to 3)

Set the number of transfers

NOTES:

1. When the DCTi register is set to 0000h, no data transfer occurs regardless of a DMA request generation.

2. Use the LDC instruction to set registers DCT0 and DCT1.

3. To set the DCT2 register, set the B flag in the FLG register to 1 (register bank 1) and write to the R0 register.

4. To set the DCT3 register, set the B flag to 1 and write to the R1 register.

Setting Range

0000h to FFFFh(1)

b15

b8 b7

b15

Symbol

DRC0(1)

DRC1(1)

DRC2 (bank1:R2)(2)

DRC3 (bank1:R3)(3)

Address

(CPU internal register)

After Reset

XXXXh

0000h

Function

DMAi Transfer Count Reload Register (i = 0 to 3)

Set the number of transfers

NOTES:

1. Use the LDC instruction to set registers DRC0 and DRC1.

2. To set the DRC2 register, set the B flag in the FLG register to 1 (register bank 1) and write to the R2 register.

3. To set the DRC3 register, set the B flag to 1 and write to the R3 register.

Setting Range

0000h to FFFFh

b8 b7

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