M32CSLASH8B datasheet(145/406 Pages) RENESAS

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M32C/8B Group

13. DMAC

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 128 of 385

Figure 13.7

DMD0 register: bits MD01 and MD00 = 00b

bits MD11 and MD10 = 00b

DMA disabled for channel 0

DMA disabled for channel 1

Write with LDC instruction

Start

i = 0, 1

NOTES:

1. When setting the DMiSL register, write a 1 to the DRQ bit.

2. When the INT interrupts are selected as a DMA request source, do not write a 1 to the DCTi register. If the DCTi register is

1, do not generate a DMA request when writing 01b or 11b to bits MDi1 and MDi0.

3. Wait six CPU clock cycles or more by a program to set bits MDi1 and MDi0 to 01b or 11b after setting the DMiSL register.

4. When a DMA transfer is started by the software trigger, set both the DSR and DRQ bit in the DMiSL register to 1 at the

same time.

DMA request source select bits

DMA requested

Set an incremented source address or

incremented destination address

Set a fixed source address or

fixed destination address

Set an incremented source address or

incremented destination address

Set the number of transfers(2)

Transfer mode select bits for channel 0

Transfer unit select bit for channel 0

Transfer direction select bit for channel 0

Transfer mode select bits for channel 1

Transfer unit select bit for channel 1

Transfer direction select bit for channel 1

End

Write with LDC instruction

(note 1)

(note 4)

Set the number of transfers, which is to be

reloaded

Write with LDC instruction

Write with LDC instruction

DMiSL register: bits DSEL4 to DSEL0

DSR bit = 0

DRQ bit = 1

DMAi register

DSAi register

DRAi register

DCTi register

DRCi register

DMD0 register: bits MD01 and MD00

BW0 bit

RW0 bit

bits MD11 and MD10

BW1 bit

RW1 bit

Start the peripheral function

used as DMAi request source

Set the peripheral function

used as DMAi request source

Set the control registers of the peripheral function,

but do not yet start.

(note 3)

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