M32CSLASH8B datasheet(147/406 Pages) RENESAS

147 / 406 page

Under development

M32C/8B Group

13. DMAC

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 130 of 385

13.1

Transfer Cycles

The transfer cycle is composed of bus cycles to read data from source address (source read) and bus cycles to write

data to destination address (destination write). The number of read and write bus cycles depends on the locations of

source and destination addresses. In memory expansion mode and microprocessor mode, the number of read and

write bus cycles also depends on DS register setting. Software wait state insertion and the RDY signal can extend

the number of the bus cycles.

13.1.1

Effect of Source and Destination Addresses

When a 16-bit data is transferred with a 16-bit data bus and a source address starts with an odd address, the

source-read cycle is added by one bus cycle, compared to a source address starting with an even address.

When a 16-bit data is transferred with a 16-bit data bus and a destination address starts with an odd address, the

destination-write cycle is added by one bus cycle, compared to a destination address starting with an even

address.

13.1.2

Effect of the DS Register

In an external space in memory expansion mode and microprocessor mode, the transfer cycle varies depending

on the data bus width of the source and destination addresses. See Figure 8.1 for details about the DS register.

• When a 16-bit data is transferred accessing both source address and destination address with an 8-bit data

bus (the DSi bit in the DS register is set to 0 (i = 0 to 3)), an 8-bit data will be transferred twice. Therefore,

two bus cycles are required for reading and another two bus cycles for writing.

• When a 16-bit data is transferred accessing a source address with an 8-bit data bus (the DSi bit is set to 0)

and a destination address with a 16-bit data bus, an 8-bit data will be read twice but be written once as 16-

bit data. Therefore, two bus cycles are required for reading and one bus cycle for writing.

• When a 16-bit data is transferred accessing a source address with a 16-bit data bus (the DSi bit is set to 1)

and a destination address with an 8-bit data bus, a 16-bit data will be read once and an 8-bit data will be

written twice. Therefore, one bus cycle is required for reading and two bus cycles for writing.

13.1.3

Effect of Software Wait State

When accessing the SFR area or memory space that requires wait states, the number of bus clocks (BCLK) is

increased by software wait states.

13.1.4

Effect of the RDY Signal

In memory expansion mode and microprocessor mode, the RDY signal affects the number of the bus cycles if a

source address or destination address is in an external space. Refer to 8.2.6 RDY Signal for details.

M32C/8B 数据表(PDF) 147 Page - Renesas Technology Corp

M32C/8B 数据表(HTML) 147 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载