M32CSLASH8B datasheet(151/406 Pages) RENESAS

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Under development

M32C/8B Group

14. DMACII

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 134 of 385

Figure 14.1

RLVL Register

b7 b6 b5 b4

Symbol

RLVL

Address

009Fh

After Reset

XXXX 0000b

Function

Bit Symbol

Bit Name

Exit Priority Register

−

RLVL0

Exit wait mode/stop mode

interrupt priority level

control bits(1)

RLVL1

RLVL2

b2 b1 b0

0 0 0: Level 0

0 0 1: Level 1

0 1 0: Level 2

0 1 1: Level 3

1 0 0: Level 4

1 0 1: Level 5

1 1 0: Level 6

1 1 1: Level 7

FSIT

DMAII

High-speed interrupt select bit

DMACII select bit(4)

0: Interrupt priority level 7 is used for interrupt

1: Interrupt priority level 7 is used for DMACII

transfer(2)

0: Interrupt priority level 7 is used for normal

interrupt

1: Interrupt priority level 7 is used for high-speed

interrupt(2)(3)

−

(b7-b6)

−

Unimplemented.

Write 0. Read as undefined value.

NOTES:

1. The MCU exits stop or wait mode when an interrupt priority level of a requested interrupt is higher than a level set using bits

RLVL2 to RLVL0. Set bits RLVL2 to RLVL0 to the same value as IPL in the FLG register.

2. Do not set both the FSIT and DMAII bits to 1.

Set either the FSIT bit or the DMAII bit to 1 before setting bits ILVL2 to ILVL0 in the Interrupt Control Register to 111b.

3. Only one interrupt can have the interrupt priority level 7 when selecting the high-speed interrupt.

4. The DMAII bit is undefined after reset. To use interrupt priority level 7 for an interrupt, set it to 0 before setting the Interrupt

Control Register.

−

(b4)

Unimplemented.

Write 0. Read as undefined value.

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