M32CSLASH8B datasheet(152/406 Pages) RENESAS

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M32C/8B Group

14. DMACII

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 135 of 385

14.1.2

DMACII Index

The DMACII index is an 8- to 32-byte data table, which stores parameters for transfer mode, transfer counter,

source address (or immediate data), operation address as an address to be calculated, destination address, chain

transfer address, and end-of-transfer interrupt address.

The DMACII index must be located on the RAM area.

Figure 14.2 shows a configuration of the DMACII index. Table 14.2 lists an example configuration of the

DMACII index.

Figure 14.2

DMACII Index

Details of the DMACII index are described below. Set these parameters in the specified order listed in Table

14.2, depending on DMACII transfer mode.

• Transfer mode (MOD)

MOD is two-byte data and required to set transfer mode. Figure 14.3 shows a configuration for transfer mode.

• Transfer counter (COUNT)

COUNT is two-byte data and required to set the number of transfer.

• Transfer source address (SADR)

SADR is two-byte data and required to set a source memory address or immediate data.

• Operation address (OADR)

OADR is two-byte data and required to set a memory address to be calculated. Set this data only when using the

calculation transfer function.

• Transfer destination address (DADR)

DADR is two-byte data and required to set a destination memory address.

• Chain transfer address (CADR)

CADR is four-byte data and required to set the starting address of the DMACII index for the next transfer. Set

this data only when using the chain transfer function.

• End-of-transfer interrupt address (IADR)

IADR is four-byte data and required to set a jump address for end-of-transfer interrupt processing. Set this data

only when using the end-of-transfer interrupt.

The abbreviations shown in parentheses( ) for each parameter are used in this section.

Multiple Transfer

Memory-to-Memory Transfer, Immediate Transfer,

Calculation Transfer

BASE+8

BASE+4

BASE+6

BASE+2

BASE+16

BASE+12

BASE+14

BASE+10

Transfer mode (MOD)

Transfer destination address (DADR)

Transfer source address (or immediate data) (SADR)

Operation address(1) (OADR)

Transfer counter (COUNT)

End-of-Transfer Interrupt Address (higher byte)(3)

(IADR1)

Chain Transfer Address (higher byte)(2) (CADR1)

End-of-Transfer Interrupt Address (lower byte)(3)

(IADR0)

Chain Transfer Address (lower byte)(2) (CADR0)

DMACII Index

Starting Address

(BASE)

16 bits

NOTES:

1. This data is not needed unless using the calculation transfer function.

2. This data is not needed unless using the chain transfer function.

3. This data is not needed unless using the end-of-transfer interrupt.

BASE+8

BASE+4

BASE+6

BASE+2

BASE+30

BASE+28

BASE+10

Transfer mode (MOD)

Transfer source address (SADR2)

Transfer source address (SADR1)

Transfer destination address (DADR1)

Transfer counter (COUNT)

Transfer destination address (DADR7)

Transfer source address (SADR7)

Transfer destination address (DADR2)

BASE

16 bits

Place the DMACII index in the RAM. Necessary data must be set top-aligned without any space. For example, if not using the

calculation transfer function, assign a transfer destination address to BASE+6.

The starting address of the DMACII index must be assigned to the interrupt vector of the peripheral function interrupt triggering

a DMACII request.

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