M32CSLASH8B datasheet(156/406 Pages) RENESAS

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M32C/8B Group

14. DMACII

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 139 of 385

14.5

Chain Transfer

The chain transfer can be selected with the CHAIN bit in MOD.

The chain transfer is performed as follows.

(1) Transfer occurs in response to an interrupt request from a peripheral function and is performed according to

the contents of the DMACII index at the address specified by the interrupt vector. For one transfer request,

either a single transfer or burst transfer selected by the BRST bit in MOD occurs.

(2) When COUNT reaches zero, the interrupt vector in (1) is replaced with the address written in CADR1 and

CADR0. The end-of-transfer interrupt occurs after the replacement, if the INTE bit in MOD is set to 1.

(3) When the next DMACII transfer request is generated, the transfer is performed according to the contents of

the DMACII index specified by the interrupt vector which has been replaced in (2).

Figure 14.4 shows the relocatable vector and DMACII index when using the chain transfer.

For the chain transfer, the relocatable vector table must be located in the RAM.

Figure 14.4

Relocatable Vector and DMACII Index When using the Chain Transfer

14.6

End-of-Transfer Interrupt

The end-of-transfer interrupt can be selected with the INTE bit in MOD. Set the starting address of the end-of-

transfer interrupt routine in IADR1 and IADR0. The end-of-transfer interrupt occurs when COUNT reaches zero.

BASE (a)

DMACII index (b)

INTB

DMACII index (a)

(CADR1,

CADR0)

BASE (b)

(CADR1,

CADR0)

Relocatable

Vector

RAM

Interrupt vector of the peripheral function triggering

DMACII request. Default value is BASE (a).

BASE (c)

BASE (b)

When COUNT reaches zero, the above interrupt

vector is replaced with BASE (b), which is the

address written in CADR1 and CADR0.

When the next request occurs, a transfer starts

according to the contents of the DMACII index at

BASE (b).

When COUNT reaches zero, the interrupt vector

is replaced wtih BASE (c).

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