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M32C/8B Group

14. DMACII

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 137 of 385

14.1.3

Interrupt Control Register for the Peripheral Function

To use the peripheral function interrupt as a DMACII request source, set bits ILVL2 to ILVL0 to 111b (level 7).

14.1.4

Relocatable Vector Table for the Peripheral Function

Set the starting address of the DMACII index in an interrupt vector for the peripheral function interrupt used as

a DMACII request source. When using the chain transfer, the relocatable vector table must be located in the

RAM.

14.2

DMACII Performance

The DMACII function is selected by setting the DMAII bit to 1 (interrupt priority level 7 is used for DMACII

transfer). DMACII transfer request is generated by interrupt requests from any peripheral function with bits ILVL2

to ILVL0 set to 111b (level 7). These peripheral function interrupt requests are used as DMACII transfer requests

and the peripheral function interrupts cannot be used.

When an interrupt request with bits ILVL2 to ILVL0 set to 111b (level 7) is generated, DMACII is activated

regardless of the I flag and IPL settings.

14.3

Transfer Data

DMACII transfers data in 8-bit units or 16-bit units.

• Memory-to-memory transfer: data is transferred from a given memory location in the 64-Kbyte space

(addresses 00000h to 0FFFFh) to another given memory location in the same space.

• Immediate data transfer: immediate data is transferred to a given memory location in the 64-Kbyte space.

• Calculation transfer: two 8-bit or two 16-bit data are added together and the result is transferred to a given

memory location in the 64-Kbyte space.

When a 16-bit data is transferred to a destination address 0FFFFh, it is transferred to addresses 0FFFFh and

10000h. Likewise, when a source address is 0FFFFh, a 16-bit data in addresses 0FFFFh and 10000h is transferred

to a given destination address.

The actual transferable space varies depending on internal RAM capacity. Refer to Figure 3.1 for the internal

memory.

14.3.1

Memory-to-memory Transfer

Data transfer between any two memory locations in the 64-Kbyte space can be:

• a transfer from a fixed address to another fixed address;

• a transfer from a fixed address to an incremented address;

• a transfer from an incremented address to a fixed address;

• a transfer from an incremented address to another incremented address.

When an incremented address is selected, DMACII increments an address after every transfer for the following

transfer. In a 8-bit data transfer, a transfer address is incremented by one. In a 16-bit data transfer, a transfer

address is incremented by two.

When a source or destination address exceeds 0FFFFh as a result of address incrementation, the source or

destination address returns to 00000h and continues incrementation. Maintain source and destination address at

0FFFFh or below.

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