M32CSLASH8B datasheet(157/406 Pages) RENESAS

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M32C/8B Group

14. DMACII

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 140 of 385

14.7

Execution Time

DMACII execution time is calculated by the following equations (single-speed mode):

Multiple transfers: t [bus clock] = 21+ (11 + b + c) × k

Other than multiple transfers: t [bus clock] = 6 + (26 + a + b + c + d) × m + (4 + e) × n

a: If IMM = 0 (source is immediate data), a = 0; if IMM = 1 (source is data in memory location), a = -1.

b: If UPDS = 1 (source address is incremented), b = 0; if UPDS = 0 (source address is fixed), b = 1.

c: If UPDD = 1 (destination address is incremented), c = 0; if UPDD = 0 (destination address is fixed), c = 1.

d: If OPER = 0 (calculation function is not selected), d = 0;

if OPER = 1 (calculation function is selected) and UPDS = 0 (source is immediate data or fixed address in

memory location), d = 7;

if OPER = 1 (calculation function is selected) and UPDS = 1 (source is incremented address in memory

location), d = 8.

e: If CHAIN = 0 (chain transfer is not selected), e = 0; if CHAIN = 1 (chain transfer is selected), e = 4.

m: If BRST = 0 (single transfer), m = 1; if BRST = 1 (burst transfer), m = a value set in COUNT.

n: If COUNT = 1, n = 0; if COUNT = 2 or more, n = 1.

k: The number of transfers set in bits CNT2 to CNT0 in MOD.

The above equations are approximations. The execution time varies depending on CPU state, bus wait states, and

DMACII index allocation.

The first instruction of the end-of-transfer interrupt routine is executed in the eighth bus clock after the DMACII

transfer is completed.

Figure 14.5

Transfer Time

When a DMACII transfer request is generated simultaneously with another request having a higher priority (e.g.,

NMI or watchdog timer), the interrupt with higher priority is acknowledged first, and the pending DMACII transfer

starts after the interrupt sequence of the higher priority interrupt has been completed.

Conditions of the example below:

-memory-to-memory transfer (a = -1)

-incremented source address (b = 0)

-fixed destination address (c = 1)

-no calculation function (d = 0)

-no chain transfer (e = 0)

-single transfer (m = 1)

-the end-of-transfer interrupt (transfer counter = 2) occurs

Transfer counter = 2

Transfer counter is decremented.

Transfer counter = 1

7 clocks

DMACII transfer

requested

Program

First DMACII transfer

t = 6 + 26 x 1 + 4 x 1 = 36 bus clocks

Second DMACII transfer t = 6 + 26 x 1 + 4 x 0 = 32 bus clocks

DMACII transfer

requested

First

DMACII transfer

End-of-transfer interrupt

routine executed

32 clocks

Program

Transfer counter = 1

Transfer counter is decremented.

Transfer counter = 0

Second

DMACII transfer

36 clocks

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