M32CSLASH8B datasheet(146/406 Pages) RENESAS

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Under development

M32C/8B Group

13. DMAC

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 129 of 385

Figure 13.8

Write with LDC instruction

DMA disabled for channel 2

DMA disabled for channel 3

DMA request source select bits

DMA requested

Transfer mode select bits for channel 2

Transfer unit select bit for channel 2

Transfer direction select bit for channel 2

Transfer mode select bits for channel 3

Transfer unit select bit for channel 3

Transfer direction select bit for channel 3

End

Select register bank 1(2)

Set an incremented source address or

incremented destination address

Write with MOV instruction

Set a fixed source address or

fixed destination address

Write with LDC instruction

DRA2 (SVP) register or DRA3 (VCT) register

Set an incremented source address or

incremented destination address

Set the number of transfer(3)

Write with MOV instruction

Set the number of transfer, which is to be

reloaded

Write with LDC instruction

(note 1)

(note 5)

i = 2, 3

NOTES:

1. When setting the DMiSL register, write a 1 to the DRQ bit.

2. The register bank 1 and high-speed interrupt cannot be used when using DMA2 and DMA3.

3. When the INT interrupts are selected as a DMA request source, do not write a 1 to the DCTi register. If the DCTi register is

1, do not generate a DMA request when writing 01b or 11b to bits MDi1 and MDi0.

4. Wait six CPU clock cycles or more by a program to set bits MDi1 and MDi0 to 01b or 11b after setting the DMiSL register.

5. When a DMA transfer is started by the software trigger, set both the DSR and DRQ bit in the DMiSL register to 1 at the

same time.

Write with MOV instruction

Write with LDC instruction

Select register bank 0(2)

DMD1 register: bits MD21 and MD20 = 00b

bits MD31 and MD30 = 00b

DMiSL register: bits DSEL4 to DSEL0

DSR bit = 0

DRQ bit = 1

B flag = 1

DMA2 (A0) register or DMA3 (A1) register

DSA2 (SB) register or DSA3 (FB) register

DMD1 register: bits MD21 and MD20

BW2 bit

RW2 bit

bits MD31 and MD30

BW3 bit

RW3 bit

Start the peripheral function

used as DMAi request source

DCT2 (R0) register or DCT3 (R1) register

DRC2 (R2) register or DRC3 (R3) register

B flag = 0

Set the peripheral function

used as DMAi request source

Set the control registers of the peripheral function,

but do not yet start.

(note 4)

Start

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