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H8S/2214 数据表(PDF) 333 Page - Renesas Technology Corp

部件名 H8S/2214
功能描述  16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series
PDF  936 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8S/2214 数据表(HTML) 333 Page - Renesas Technology Corp

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Section 8 Data Transfer Controller (DTC)
Rev.4.00 Sep. 18, 2008 Page 273 of 872
REJ09B0189-0400
8.3.8
Chain Transfer
Setting the CHNE bit to 1 enables a number of data transfers to be performed consectutively in
response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data
transfers, can be set independently.
Figure 8.9 shows the memory map for chain transfer. The DTC reads the start address for the
register information from the DTC vector address corresponding to the DTC activation factor.
After the data transfer completes, the CHNE bit in this register is tested, and if it is 1, the next
register information allocated sequentially is read and a transfer is performed. This operation
continues until a data transfer for register information whose CHNE bit is 0 completes.
Source
Source
Destination
Destination
DTC vector
address
Register information
start address
Register information
CHNE = 1
Register information
CHNE = 0
Figure 8.9 Chain Transfer Memory Map
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.



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