H8SSLASH2214 datasheet(357/936 Pages) RENESAS

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Section 9 I/O Ports

Rev.4.00 Sep. 18, 2008 Page 297 of 872

REJ09B0189-0400

9.3.2

Table 9.4 shows the port 3 register configuration.

Table 9.4

Port 3 Registers

Name

Abbreviation

R/W

Initial Value*

Address*

Port 3 data direction register

P3DDR

H'00

H'FE32

Port 3 data register

P3DR

R/W

H'00

H'FF02

Port 3 register

PORT3

H'00

H'FFB2

Port 3 open-drain control register

P3ODR

R/W

H'00

H'FE46

Interrupt request input pin select register 0 IPINTSEL0

R/W

H'00

H'FE4A

Notes: 1. Lower 16 bits of the address.

2. Value of bits 6 to 0.

(1) Port 3 Data Direction Register (P3DDR)

—

Undefined

—

P36DDR

P35DDR

P34DDR

P33DDR

P30DDR

P32DDR

P31DDR

Bit

Initial value :

R/W

P3DDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port 3. P3DDR cannot be read; if it is, an undefined value will be returned. Bit 7 is

reserved; this bit cannot be modified and will return an undefined value if read.

Setting a P3DDR bit to 1 makes the corresponding port 3 pin an output pin, while clearing the bit

to 0 makes the pin an input pin.

Since this register is a write-only register, do not use bit manipulation instructions to write to this

P3DDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its

previous state after a manual reset and in software standby mode. As the SCI is initialized by a

manual reset, the pin states in this case are determined by the P3DDR and P3DR specifications.

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