H8SSLASH2214 datasheet(359/936 Pages) RENESAS

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Section 9 I/O Ports

Rev.4.00 Sep. 18, 2008 Page 299 of 872

REJ09B0189-0400

(4) Port 3 Open-Drain Control Register (P3ODR)

—

Undefined

—

P36ODR

R/W

P35ODR

R/W

P34ODR

R/W

P33ODR

R/W

P30ODR

R/W

P32ODR

R/W

P31ODR

R/W

Bit

Initial value :

R/W

P3ODR is an 8-bit readable/writable register that controls the PMOS on/off status for each port 3

pin (P36 to P30). Bit 7 is reserved; this bit cannot be modified and will return an undefined value

if read.

Setting a P3ODR bit to 1 makes the corresponding port 3 pin an NMOS open-drain output pin,

while clearing the bit to 0 makes the pin a CMOS output pin.

P3ODR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its

previous state after a manual reset and in software standby mode.

(5) Interrupt Request Input Pin Select Register 0 (IPINSEL0)

Bit

P36

IRQ7E

P47

IRQ6E

P46

IRQ5E

P44

IRQ4E

P43

IRQ3E

P42

IRQ2E

P41

IRQ1E

P40

IRQ0E

Initial value :

R/W

IPINSEL0 is an 8-bit readable/writable register that selects which pins are to be used for interrupt

request input signals (

EXIRQ0 to EXIRQ7) from externally connected modules. IPINSEL0 is

initialized to H'00 by a power-on reset and in hardware standby mode. It retains its previous state

in a manual reset and in software standby mode.

Bit 7—Enable of

EXIRQ7 Input from P36 (P36IRQ7E): Selects whether or not P36 is used as

the

EXIRQ7 input pin.

Bit 7

P36IRQ7E

Description

P36 is not used as

EXIRQ7 input

(Initial value)

P36 is used as

EXIRQ7 input

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