H8SSLASH2214 datasheet(428/936 Pages) RENESAS

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Section 10 16-Bit Timer Pulse Unit (TPU)

Rev.4.00 Sep. 18, 2008 Page 368 of 872

REJ09B0189-0400

Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge.

When the input clock is counted using both edges, the input clock period is halved (e.g.

φ/4 both

edges =

φ/2 rising edge). If phase counting mode is used on channels 1 and 2, this setting is

ignored and the phase counting mode setting has priority.

Bit 4

Bit 3

CKEG1

CKEG0

Description

Count at rising edge

(Initial value)

Count at falling edge

—

Count at both edges

Note:

Internal clock edge selection is valid when the input clock is

φ/4 or slower. This setting is

ignored if the input clock is

φ/1, or when overflow/underflow of another channel is selected.

(Counting occurs on the falling edge of

φ when φ/1 is selected.)

Bits 2 to 0—Time Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the TCNT counter

clock. The clock source can be selected independently for each channel. Table 10.4 shows the

clock sources that can be set for each channel.

Table 10.4

TPU Clock Sources

Channel

Internal Clock

External Clock

Channel

φ/1

φ/4

φ/16

φ/64

φ/256

φ/1024 φ/4096

TCLKA TCLKB TCLKC TCLKD

Legend:

Setting

Blank: No setting

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