H8SSLASH2214 datasheet(431/936 Pages) RENESAS

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Section 10 16-Bit Timer Pulse Unit (TPU)

Rev.4.00 Sep. 18, 2008 Page 371 of 872

REJ09B0189-0400

Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or

TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer

In channels 1 and 2 which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be

modified.

Bit 4

BFA

Description

TGRA operates normally

(Initial value)

TGRA and TGRC used together for buffer operation

Bits 3 to 0—Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode.

Bit 3

Bit 2

Bit 1

Bit 0

MD3

MD2

MD1

MD0

Description

Normal operation

(Initial value)

Reserved

PWM mode 1

PWM mode 2

Phase counting mode 1

Phase counting mode 2

Phase counting mode 3

Phase counting mode 4

—

Legend:

*: Don’t care

Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0.

2. Phase counting mode cannot be set for channel 0. In this case, 0 should always be

written to MD2.

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