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H8S/2214 数据表(PDF) 461 Page - Renesas Technology Corp |
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H8S/2214 数据表(HTML) 461 Page - Renesas Technology Corp |
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461 / 936 page  Section 10 16-Bit Timer Pulse Unit (TPU) Rev.4.00 Sep. 18, 2008 Page 401 of 872 REJ09B0189-0400 10.4.4 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 10.5 shows the register combinations used in buffer operation. Table 10.5 Register Combinations in Buffer Operation Channel Timer General Register Buffer Register 0 TGR0A TGR0C TGR0B TGR0D • When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 10.16. Buffer register Timer general register TCNT Comparator Compare match signal Figure 10.16 Compare Match Buffer Operation |
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