H8SSLASH2214 datasheet(463/936 Pages) RENESAS

部件名	H8S/2214

功能描述	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	936 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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Section 10 16-Bit Timer Pulse Unit (TPU)

Rev.4.00 Sep. 18, 2008 Page 403 of 872

REJ09B0189-0400

(2) Examples of Buffer Operation

• When TGR is an output compare register

Figure 10.19 shows an operation example in which PWM mode 1 has been designated for

channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used

in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0

output at compare match B.

As buffer operation has been set, when compare match A occurs the output changes and the

value in buffer register TGRC is simultaneously transferred to timer general register TGRA.

This operation is repeated each time compare match A occurs.

For details of PWM modes, see section 10.4.5, PWM Modes.

TCNT value

TGR0B

H'0000

TGR0C

Time

TGR0A

H'0200

H'0520

TIOCA

H'0200

H'0450

H'0520

H'0450

TGR0A

H'0450

H'0200

Transfer

Figure 10.19 Example of Buffer Operation (1)

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