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H8S/2214 数据表(PDF) 486 Page - Renesas Technology Corp |
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H8S/2214 数据表(HTML) 486 Page - Renesas Technology Corp |
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486 / 936 page ![]() Section 10 16-Bit Timer Pulse Unit (TPU) Rev.4.00 Sep. 18, 2008 Page 426 of 872 REJ09B0189-0400 (4) Status Flag Clearing Timing After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 10.42 shows the timing for status flag clearing by the CPU, and figure 10.43 shows the timing for status flag clearing by the DTC or DMAC. Status flag Write signal Address φ TSR address Interrupt request signal TSR write cycle T1 T2 Figure 10.42 Timing for Status Flag Clearing by CPU Interrupt request signal Status flag Address φ Source address DTC/DMAC read cycle T1 T2 Destination address T1 T2 DTC/DMAC write cycle Figure 10.43 Timing for Status Flag Clearing by DTC/DMAC Activation |
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