H8SSLASH2214 datasheet(487/936 Pages) RENESAS

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Section 10 16-Bit Timer Pulse Unit (TPU)

Rev.4.00 Sep. 18, 2008 Page 427 of 872

REJ09B0189-0400

10.7

Usage Notes

Note that the kinds of operation and contention described below occur during TPU operation.

(1) Module Stop Mode Settings

The TPU module operation disabled/enabled state can be set with the module stop control register.

The initial value of this register sets the TPU module to the stopped state. Register access becomes

possible when module stop mode is cleared. See section 17, Power-Down Modes, for details.

(2) Input Clock Restrictions

The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at

least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a

narrower pulse width.

In phase counting mode, the phase difference and overlap between the two input clocks must be at

least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.44 shows the input clock

conditions in phase counting mode.

Overlap

Phase

differ-

ence

Phase

differ-

ence

Overlap

TCLKA

(TCLKC)

TCLKB

(TCLKD)

Pulse width

Notes: Phase difference and overlap

Pulse width

: 1.5 states or more

: 2.5 states or more

Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode

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