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H8S/2214 数据表(PDF) 491 Page - Renesas Technology Corp

部件名 H8S/2214
功能描述  16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series
PDF  936 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8S/2214 数据表(HTML) 491 Page - Renesas Technology Corp

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Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.4.00 Sep. 18, 2008 Page 431 of 872
REJ09B0189-0400
(7) Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T
2 state of a TGR write cycle, the data transferred to TGR by the
buffer operation will be the data prior to the write.
Figure 10.48 shows the timing in this case.
Compare
match signal
Write signal
Address
φ
Buffer register
address
Buffer
register
TGR write cycle
T1
T2
N
TGR
N
M
Buffer register write data
Figure 10.48 Contention between Buffer Register Write and Compare Match



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