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H8S/2214 数据表(PDF) 493 Page - Renesas Technology Corp |
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H8S/2214 数据表(HTML) 493 Page - Renesas Technology Corp |
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493 / 936 page ![]() Section 10 16-Bit Timer Pulse Unit (TPU) Rev.4.00 Sep. 18, 2008 Page 433 of 872 REJ09B0189-0400 (9) Contention between TGR Write and Input Capture If the input capture signal is generated in the T 2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 10.50 shows the timing in this case. Input capture signal Write signal Address φ TCNT TGR write cycle T1 T2 M TGR M TGR address Figure 10.50 Contention between TGR Write and Input Capture |
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