H8SSLASH2214 datasheet(119/936 Pages) RENESAS

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Section 2 CPU

Rev.4.00 Sep. 18, 2008 Page 59 of 872

REJ09B0189-0400

(2) Reset Exception Handling

After the

RES or MRES pin has gone low and the reset state has been entered, reset exception

handling starts when

RES or MRES goes high again. The CPU enters the power-on reset state

when the

RES pin is low, and the manual reset state when the MRES pin is low. When reset

exception handling starts the CPU fetches a start address (vector) from the exception vector table

and starts program execution from that address. All interrupts, including NMI, are disabled during

reset exception handling and after it ends.

(3) Traces

Traces are enabled only in interrupt control mode 2. Trace mode is entered when the T bit of EXR

is set to 1. When trace mode is established, trace exception handling starts at the end of each

instruction.

At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode

is cleared. Interrupt masks are not affected.

The T bit saved on the stack retains its value of 1, and when the RTE instruction is executed to

return from the trace exception-handling routine, trace mode is entered again. Trace exception-

handling is not executed at the end of the RTE instruction.

Trace mode is not entered in interrupt control mode 0, regardless of the state of the T bit.

(4) Interrupt Exception Handling and Trap Instruction Exception Handling

When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer

(ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU

alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start

address (vector) from the exception vector table and program execution starts from that start

address.

Figure 2.17 shows the stack after exception handling ends.

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