H8SSLASH2214 datasheet(121/936 Pages) RENESAS

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Section 2 CPU

Rev.4.00 Sep. 18, 2008 Page 61 of 872

REJ09B0189-0400

2.8.4

Program Execution State

In this state the CPU executes program instructions in sequence.

2.8.5

Bus-Released State

This is a state in which the bus has been released in response to a bus request from a bus master

other than the CPU. While the bus is released, the CPU halts operations.

There are two other bus masters in addition to the CPU: the DMA controller (DMAC) and data

transfer controller (DTC).

For further details, refer to section 6, Bus Controller.

2.8.6

Power-Down State

The power-down state includes both modes in which the CPU stops operating and modes in which

the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode,

software standby mode, and hardware standby mode. There are also three other power-down

modes: medium-speed mode, module stop mode, and subactive mode. In medium-speed mode the

CPU and other bus masters operate on a medium-speed clock. Module stop mode permits halting

of the operation of individual modules, other than the CPU. For details, refer to section 17, Power-

Down Modes.

(1) Sleep Mode

A transition to sleep mode is made if the SLEEP instruction is executed while the SSBY bit in

SBYCR and the LSON bit in LPWRCR are both cleared to 0. In sleep mode, CPU operations stop

immediately after execution of the SLEEP instruction. The contents of CPU registers are retained.

(2) Software Standby Mode

A transition to software standby mode is made if the SLEEP instruction is executed while the

SSBY bit in SBYCR is set to 1, and the LSON bit in LPWRCR and the PSS bit in TCSR (WDT1)

are both cleared to 0. In software standby mode, the CPU and clock halt and all MCU operations

stop. As long as a specified voltage is supplied, the contents of CPU registers and on-chip RAM

are retained. The I/O ports also remain in their existing states.

(3) Hardware Standby Mode

A transition to hardware standby mode is made when the

STBY pin goes low. In hardware

standby mode, the CPU and clock halt and all MCU operations stop. The on-chip supporting

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