H8SSLASH2214 datasheet(139/936 Pages) RENESAS

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Section 4 Exception Handling

Rev.4.00 Sep. 18, 2008 Page 79 of 872

REJ09B0189-0400

Section 4 Exception Handling

4.1

Overview

4.1.1

Exception Handling Types and Priority

As table 4.1 indicates, exception handling may be caused by a reset, trace, trap instruction, or

interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur

simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions

are accepted at all times, in the program execution state.

Exception handling sources, the stack structure, and the operation of the CPU vary depending on

the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR.

Table 4.1

Exception Handling Types and Priority

Priority

Exception Handling Type

Start of Exception Handling

High

Reset

Starts immediately after a low-to-high transition at the

RES or MRES pin, or when the watchdog timer

overflows. The CPU enters the power-on reset state

when the

RES pin is low, and the manual reset state

when the

MRES pin is low.

Trace*

Starts when execution of the current instruction or

exception handling ends, if the trace (T) bit is set to 1

Interrupt

Starts when execution of the current instruction or

exception handling ends, if an interrupt request has

been issued*

Low

Trap instruction (TRAPA)*

Started by execution of a trap instruction (TRAPA)

Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not

executed after execution of an RTE instruction.

2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC

instruction execution, or on completion of reset exception handling.

3. Trap instruction exception handling requests are accepted at all times in program

execution state.

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