H8SSLASH2214 datasheet(136/936 Pages) RENESAS

136 / 936 page

Section 3 MCU Operating Modes

Rev.4.00 Sep. 18, 2008 Page 76 of 872

REJ09B0189-0400

The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16-

bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and

port E becomes a data bus.

3.3.3

Mode 6

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.

Pins P13 to P10, and ports A and B function as input ports immediately after a reset. Address

(A23 to A8) output can be enabled or disabled by bits AE3 to AE0 in the pin function control

which address output is disabled among pins P13 to P10 and in ports A and B become port outputs

when the corresponding DDR bits are set to 1.

Ports D and E function as a data bus, and part of port F carries data bus signals.

Port C is an input port immediately after a reset. Addresses A7 to A0 are output by setting the

corresponding DDR bits to 1.

The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16-

bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and

port E becomes a data bus.

3.3.4

Mode 7

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled,

but external addresses cannot be accessed.

All I/O ports are available for use as input-output ports.

H8S/2214 数据表(PDF) 136 Page - Renesas Technology Corp