H8SSLASH2214 datasheet(133/936 Pages) RENESAS

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Section 3 MCU Operating Modes

Rev.4.00 Sep. 18, 2008 Page 73 of 872

REJ09B0189-0400

levels are latched into these bits when MDCR is read. These latches are canceled by a power-on

reset, but are retained after a manual reset.

3.2.2

System Control Register (SYSCR)

—

R/W

—

INTM1

R/W

INTM0

R/W

NMIEG

R/W

RAME

R/W

MRESE

R/W

—

Bit

Initial value

R/W

SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, the detected

edge for NMI, and enables or disables

MRES pin input and on-chip RAM.

SYSCR is initialized to H'01 by a power-on reset and in hardware standby mode. In a manual

reset, the INTM1, INTM0, NMIEG, and RAME bits are initialized, but the MRESE bit is not.

SYSCR is not initialized in software standby mode.

Bit 7—Reserved: Only 0 should be written to this bit.

Bit 6—Reserved: Read-only bit, always read as 0.

Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control

mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1,

Interrupt Control Modes and Interrupt Operation.

Bit 5

Bit 4

Interrupt

INTM1

INTM0

Control Mode

Description

Control of interrupts by I bit

(Initial value)

—

Setting prohibited

Control of interrupts by I2 to I0 bits and IPR

—

Setting prohibited

Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input.

Bit 3

NMIEG

Description

An interrupt is requested at the falling edge of NMI input

(Initial value)

An interrupt is requested at the rising edge of NMI input

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