H8SSLASH2214 datasheet(222/936 Pages) RENESAS

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Section 6 Bus Controller

Rev.4.00 Sep. 18, 2008 Page 162 of 872

REJ09B0189-0400

6.7.5

Usage Note

When MSTPCR is set to H'FFFFFF and a transition is made to sleep mode, the external bus

release function halts. Therefore, MSTPCR should not be set to H'FFFFFF if the external bus

release function is to be used in sleep mode.

6.8

Bus Arbitration

6.8.1

Overview

The H8S/2214 Group has a bus arbiter that arbitrates bus master operations.

There are three bus masters, the CPU, DMAC, and DTC, which perform read/write operations

when they have possession of the bus. Each bus master requests the bus by means of a bus request

signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by

means of a bus request acknowledge signal. The selected bus master then takes possession of the

bus and begins its operation.

6.8.2

Operation

The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a bus

request acknowledge signal to the bus master making the request. If there are bus requests from

more than one bus master, the bus request acknowledge signal is sent to the one with the highest

priority. When a bus master receives the bus request acknowledge signal, it takes possession of the

bus until that signal is canceled.

The order of priority of the bus masters is as follows:

(High) DMAC > DTC > CPU (Low)

An internal bus access by an internal bus master, and external bus release, can be executed in

parallel.

In the event of simultaneous external bus release request, and internal bus master external access

request generation, the order of priority is as follows:

(High) External bus release > Internal bus master external access (Low)

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