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H8S/2214 数据表(PDF) 231 Page - Renesas Technology Corp |
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H8S/2214 数据表(HTML) 231 Page - Renesas Technology Corp |
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231 / 936 page ![]() Section 6 Bus Controller Rev.4.00 Sep. 18, 2008 Page 171 of 872 REJ09B0189-0400 6.10.7 Basic Timing Figure 6.22 shows the timing of external module area (H'FFFF40 to H'FFFF5F) DTC data transfer using 3-state access. T1 T2 T3 T1 T2 T3 EXMS EXDTCE RD T1 T2 T3 T1 T2 T3 External module area read Write φ Address EXMS EXDTCE WR φ Address (a) Timing of external module area read by DTC Read External module area write (b) Timing of external module area write by DTC Figure 6.22 Timing of External Module Area Access by DTC |
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