H8SSLASH2214 datasheet(235/936 Pages) RENESAS

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Section 7 DMA Controller

Rev.4.00 Sep. 18, 2008 Page 175 of 872

REJ09B0189-0400

7.1.3

Overview of Functions

Tables 7.1 and 7.2 summarize DMAC functions in short address mode and full address mode,

respectively.

Table 7.1

Overview of DMAC Functions (Short Address Mode)

Address Register Bit Length

Transfer Mode

Transfer Source

Source

Destination

Dual address mode

• Sequential mode

⎯ 1-byte or 1-word transfer

executed for one transfer request

⎯ Memory address

incremented/decremented by 1

or 2

⎯ 1 to 65536 transfers

• Idle mode

⎯ 1-byte or 1-word transfer

executed for one transfer request

⎯ Memory address fixed

⎯ 1 to 65536 transfers

• Repeat mode

⎯ 1-byte or 1-word transfer

executed for one transfer request

⎯ Memory address incremented/

decremented by 1 or 2

⎯ After specified number of

transfers (1 to 256), initial state is

restored and operation continues

• TPU channel 0 to

2 compare

match/input

capture A interrupt

• SCI transmission

complete interrupt

• SCI reception

complete interrupt

• External request

24/16

16/24

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