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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8S/2214 数据表(PDF) 239 Page - Renesas Technology Corp |
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H8S/2214 数据表(HTML) 239 Page - Renesas Technology Corp |
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239 / 936 page  Section 7 DMA Controller Rev.4.00 Sep. 18, 2008 Page 179 of 872 REJ09B0189-0400 7.2 Register Descriptions (1) (Short Address Mode) Short address mode transfer can be performed for channels A and B independently. Short address mode transfer is specified for each channel by clearing the FAE bit in DMABCR to 0, as shown in table 7.5. Short address mode or full address mode can be selected for channels 1 and 0 independently by means of bits FAE1 and FAE0. Table 7.5 Short Address Mode and Full Address Mode (For 1 Channel: Example of Channel 0) FAE0 Description 0 Short address mode specified (channels A and B operate independently) MAR0A Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source, etc. Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source, etc. IOAR0A ETCR0A DMACR0A MAR0B IOAR0B ETCR0B DMACR0B 1 Full address mode specified (channels A and B operate in combination) MAR0A Specifies transfer source address Specifies transfer destination address Not used Not used Specifies number of transfers Specifies number of transfers (used in block transfer mode only) Specifies transfer size, mode, activation source, etc. IOAR0A ETCR0A DMACR0A MAR0B IOAR0B ETCR0B DMACR0B |
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