H8SSLASH2214 datasheet(240/936 Pages) RENESAS | 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

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H8S/2214 数据表(PDF) 240 Page - Renesas Technology Corp

部件名	H8S/2214

功能描述	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	936 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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H8S/2214 数据表(HTML) 240 Page - Renesas Technology Corp

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H8S/2214 Datasheet HTML 240Page - Renesas Technology Corp

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Section 7 DMA Controller

Rev.4.00 Sep. 18, 2008 Page 180 of 872

REJ09B0189-0400

7.2.1

Memory Address Register (MAR)

Bit

:

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

MAR

:

—

—

—

—

—

—

—

—

Initial value :

0

0

0

0

0

0

0

0

*

*

*

*

*

*

*

*

R/W

:

—

—

—

—

—

—

—

— R/W R/W R/W R/W R/W R/W R/W R/W

Bit

:

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MAR

:

Initial value :

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

R/W

: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

*: Undefined

MAR is a 32-bit readable/writable register that specifies the transfer source address or destination

address.

The upper 8 bits of MAR are reserved: they are always read as 0, and cannot be modified.

Whether MAR functions as the source address register or as the destination address register can be

selected by means of the DTDIR bit in DMACR.

MAR is incremented or decremented each time a byte or word transfer is executed, so that the

address specified by MAR is constantly updated. For details, see section 7.2.4, DMA Control

Register (DMACR).

MAR is not initialized by a reset or in standby mode.

7.2.2

I/O Address Register (IOAR)

Bit

:

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

IOAR

:

Initial value :

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

R/W

: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

*: Undefined

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