H8SSLASH2214 datasheet(259/936 Pages) RENESAS

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Section 7 DMA Controller

Rev.4.00 Sep. 18, 2008 Page 199 of 872

REJ09B0189-0400

Bits 13 and 12—Reserved: This bit is reserved and only 0 can be written to, writing 1 causes a

malfunction error.

Bits 11 and 9—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when

DMA transfer is performed, of the internal interrupt source selected by the data transfer factor

setting.

When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor

setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal

interrupt source selected by the data transfer factor setting does not issue an interrupt request to the

CPU or DTC.

When the DTE = 1 and the DTA = 0, the internal interrupt source selected by the data transfer

factor setting is not cleared when a transfer is performed, and can issue an interrupt request to the

CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC

transfer.

When the DTE = 0, the internal interrupt source selected by the data transfer factor setting issues

an interrupt request to the CPU or DTC regardless of the DTA bit setting.

The state of the DTME bit does not affect the above operations.

Bit 11—Data Transfer Acknowledge 1 (DTA1B): Enables or disables clearing, when DMA

transfer is performed, of the internal interrupt source selected by the channel 1 data transfer factor

setting.

Bit 11

DTA1B

Description

Clearing of selected internal interrupt source at time of DMA transfer is disabled

(Initial value)

Clearing of selected internal interrupt source at time of DMA transfer is enabled

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