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H8S/2214 数据表(PDF) 260 Page - Renesas Technology Corp |
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H8S/2214 数据表(HTML) 260 Page - Renesas Technology Corp |
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260 / 936 page ![]() Section 7 DMA Controller Rev.4.00 Sep. 18, 2008 Page 200 of 872 REJ09B0189-0400 Bit 9—Data Transfer Acknowledge 0 (DTA0B): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0 data transfer factor setting. Bit 9 DTA0B Description 0 Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) 1 Clearing of selected internal interrupt source at time of DMA transfer is enabled Bits 10 and 8—Reserved (DTA1A, DTA0A): Reserved bits in full address mode. Although these bits are readable/writable, only 0 should be written here. Bits 7 and 5—Data Transfer Master Enable (DTME): Together with the DTE bit, these bits control enabling or disabling of data transfer on the relevant channel. When both the DTME bit and the DTE bit are set to 1, transfer is enabled for the channel. If the relevant channel is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME bit is cleared, the transfer is interrupted, and bus mastership passes to the CPU. When the DTME bit is subsequently set to 1 again, the interrupted transfer is resumed. In block transfer mode, however, the DTME bit is not cleared by an NMI interrupt, and transfer is not interrupted. The conditions for the DTME bit being cleared to 0 are as follows: • When initialization is performed • When NMI is input in burst mode • When 0 is written to the DTME bit The condition for DTME being set to 1 is as follows: • When 1 is written to DTME after DTME is read as 0 Bit 7—Data Transfer Master Enable 1 (DTME1): Enables or disables data transfer on channel 1. Bit 7 DTME1 Description 0 Data transfer disabled. In burst mode, cleared to 0 by an NMI interrupt (Initial value) 1 Data transfer enabled |
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