H8SSLASH2214 datasheet(292/936 Pages) RENESAS

部件名	H8S/2214

功能描述	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	936 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

标志

292 / 936 page

Section 7 DMA Controller

Rev.4.00 Sep. 18, 2008 Page 232 of 872

REJ09B0189-0400

7.5.8

Basic DMAC Bus Cycles

An example of the basic DMAC bus cycle timing is shown in figure 7.15. In this example, word-

size transfer is performed from 16-bit , 2-state access space to 8-bit, 3-state access space. When

the bus is transferred from the CPU to the DMAC, a source address read and destination address

write are performed. The bus is not released in response to another bus request, etc., between these

read and write operations. As with CPU cycles, DMA cycles conform to the bus controller

settings.

The address is not output to the external address bus in an access to on-chip memory or an internal

I/O register.

Address bus

DMAC cycle (1-word transfer)

LWR

HWR

Source

address

Destination address

CPU cycle

Figure 7.15 Example of DMA Transfer Bus Timing

H8S/2214 数据表(PDF) 292 Page - Renesas Technology Corp