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H8S/2214 数据表(PDF) 288 Page - Renesas Technology Corp |
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H8S/2214 数据表(HTML) 288 Page - Renesas Technology Corp |
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288 / 936 page ![]() Section 7 DMA Controller Rev.4.00 Sep. 18, 2008 Page 228 of 872 REJ09B0189-0400 Acquire bus ETCRAL = ETCRAL – 1 Transfer request? ETCRAL = H'00 Release bus BLKDIR = 0 ETCRAL = ETCRAH ETCRB = ETCRB – 1 ETCRB = H'0000 Start (DTE = DTME = 1) Read address specified by MARA MARA = MARA + SAIDE · (–1)SAID · 2DTSZ Write to address specified by MARB MARB = MARB + DAIDE · (–1)DAID · 2DTSZ MARB = MARB – DAIDE · (–1)DAID · 2DTSZ · ETCRAH MARA = MARA – SAIDE · (–1)SAID · 2DTSZ · ETCRAH No Yes No Yes No Yes No Yes Clear DTE bit to 0 to end transfer Figure 7.13 Operation Flow in Block Transfer Mode Transfer requests (activation sources) consist of external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 2 compare match/input capture A interrupts. |
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