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H8S/2214 数据表(PDF) 285 Page - Renesas Technology Corp |
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H8S/2214 数据表(HTML) 285 Page - Renesas Technology Corp |
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285 / 936 page ![]() Section 7 DMA Controller Rev.4.00 Sep. 18, 2008 Page 225 of 872 REJ09B0189-0400 Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. Whether a block is to be designated for MARA or for MARB is specified by the BLKDIR bit in DMACRA. To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL, and N in ETCRB. Figure 7.11 illustrates operation in block transfer mode when MARB is designated as a block area. Address TA Address BA Transfer Address TB Address BB 1st block 2nd block Nth block Block area Consecutive transfer of M bytes or words is performed in response to one request Legend: Address Address Address Address Where : = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (M · N – 1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (N – 1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL TA TB BA BB LA LB N M Figure 7.11 Operation in Block Transfer Mode (BLKDIR = 0) |
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