H8SSLASH2214 datasheet(284/936 Pages) RENESAS

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Section 7 DMA Controller

Rev.4.00 Sep. 18, 2008 Page 224 of 872

REJ09B0189-0400

7.5.6

Block Transfer Mode

In block transfer mode, transfer is performed with channels A and B used in combination. Block

transfer mode can be specified by setting the FAE bit in DMABCR and the BLKE bit in

DMACRA to 1.

In block transfer mode, a transfer of the specified block size is carried out in response to a single

transfer request, and this is executed the specified number of times. The transfer source is

specified by MARA, and the transfer destination by MARB. Either the transfer source or the

transfer destination can be selected as a block area (an area composed of a number of bytes or

words).

Table 7.11 summarizes register functions in block transfer mode.

Table 7.11

Function

Initial Setting

Operation

MARA

Source address

Start address of

transfer source

Incremented/decremented

every transfer, or fixed

MARB

Destination

address register

Start address of

transfer destination

Incremented/decremented

every transfer, or fixed

ETCRAH

ETCRAL

Holds block

size

Block size

counter

Block size

Fixed

Decremented every

transfer; ETCRH value

copied when count reaches

H'00

ETCRB

Block transfer

counter

Number of block

transfers

Decremented every block

transfer; transfer ends

when count reaches

H'0000

Legend:

MARA: Memory address register A

MARB: Memory address register B

ETCRA: Transfer count register A

ETCRB: Transfer count register B

MARA and MARB specify the start addresses of the transfer source and transfer destination,

respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or

word is transferred, or can be fixed.

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