H8SSLASH2214 datasheet(308/936 Pages) RENESAS

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Section 7 DMA Controller

Rev.4.00 Sep. 18, 2008 Page 248 of 872

REJ09B0189-0400

(b) If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC

[2]

[1]

Note: The lower word of MAR is the updated value after the operation in [1].

CPU longword read

DMA transfer cycle

MAR upper

word read

MAR lower

word read

DMA read

DMA write

DMA internal

address

DMA control

DMA register

operation

Transfe

source

Transfer

destination

Idle

Read

Write

Idle

Figure 7.30 Contention between DMAC Register Update and CPU Read

(2) Module Stop

When the MSTPA7 bit in MSTPCR is set to 1, the DMAC clock stops, and the module stop state

is entered. However, 1 cannot be written to the MSTPA7 bit if any of the DMAC channels is

enabled. This setting should therefore be made when DMAC operation is stopped.

When the DMAC clock stops, DMAC register accesses can no longer be made. Since the

following DMAC register settings are valid even in the module stop state, they should be

invalidated, if necessary, before a module stop.

• Transfer end/suspend interrupt (DTE = 0 and DTIE = 1)

• TEND pin enable (TEE = 1)

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