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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8S/2214 数据表(PDF) 312 Page - Renesas Technology Corp |
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H8S/2214 数据表(HTML) 312 Page - Renesas Technology Corp |
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312 / 936 page  Section 8 Data Transfer Controller (DTC) Rev.4.00 Sep. 18, 2008 Page 252 of 872 REJ09B0189-0400 8.1.2 Block Diagram Figure 8.1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information. Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1. Interrupt request Interrupt controller DTC Internal address bus CPU interrupt request On-chip RAM Internal data bus Legend: MRA, MRB: CRA, CRB: SAR: DAR: DTCERA to DTCERF, DTCERI: DTVECR: DTC mode registers A and B DTC transfer count registers A and B DTC source address register DTC destination address register DTC enable registers A to F and I DTC vector register Figure 8.1 Block Diagram of DTC |
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