H8SSLASH2214 datasheet(319/936 Pages) RENESAS

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Section 8 Data Transfer Controller (DTC)

Rev.4.00 Sep. 18, 2008 Page 259 of 872

REJ09B0189-0400

8.2.7

DTC Enable Register (DTCER)

DTCE7

R/W

DTCE6

R/W

DTCE5

R/W

DTCE4

R/W

DTCE3

R/W

DTCE0

R/W

DTCE2

R/W

DTCE1

R/W

Bit

Initial value

R/W

The DTC enable registers comprise seven 8-bit readable/writable registers, DTCERA to

DTCERG, with bits corresponding to the interrupt sources that can control enabling and disabling

of DTC activation. These bits enable or disable DTC service for the corresponding interrupt

sources.

The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode.

Bit n—DTC Activation Enable (DTCEn)

Bit n

DTCEn

Description

DTC activation by this interrupt is disabled

(Initial value)

[Clearing conditions]

• When the DISEL bit is 1 and the data transfer has ended

• When the specified number of transfers have ended

DTC activation by this interrupt is enabled

[Holding condition]

• When the DISEL bit is 0 and the specified number of transfers have not ended

(n = 7 to 0)

A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence

between interrupt sources and DTCE bits is shown in table 8.4, together with the vector number

generated for each interrupt controller.

For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and

writing. If all interrupts are masked, multiple activation sources can be set at one time by writing

data after executing a dummy read on the relevant register.

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