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H8S/2214 数据表(PDF) 321 Page - Renesas Technology Corp |
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H8S/2214 数据表(HTML) 321 Page - Renesas Technology Corp |
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321 / 936 page ![]() Section 8 Data Transfer Controller (DTC) Rev.4.00 Sep. 18, 2008 Page 261 of 872 REJ09B0189-0400 8.2.9 Module Stop Control Register A (MSTPCRA) 7 MSTPA7 0 R/W Bit : Initial value : R/W : 6 MSTPA6 0 R/W 5 MSTPA5 1 R/W 4 MSTPA4 1 R/W 3 MSTPA3 1 R/W 2 MSTPA2 1 R/W 1 MSTPA1 1 R/W 0 MSTPA0 1 R/W MSTPCRA is an 8-bit readable/writable register that performs module stop mode control. When the MSTPA6 bit in MSTPCRA is set to 1, the DTC operation stops at the end of the bus cycle and a transition is made to module stop mode. However, 1 cannot be written in the MSTPA6 bit while the DTC is operating. For details, see section 17.5, Module Stop Mode. MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 6—Module Stop (MSTPA6): Specifies the DTC module stop mode. Bit 6 MSTPA6 Description 0 DTC module stop mode cleared (Initial value) 1 DTC module stop mode set |
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