H8SSLASH2214 datasheet(324/936 Pages) RENESAS

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Section 8 Data Transfer Controller (DTC)

Rev.4.00 Sep. 18, 2008 Page 264 of 872

REJ09B0189-0400

8.3.2

Activation Sources

The DTC operates when activated by an interrupt or by a write to DTVECR by software. An

interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER

bit. An interrupt becomes a DTC activation source when the corresponding bit is set to 1, and a

CPU interrupt source when the bit is cleared to 0.

At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the

activation source or corresponding DTCER bit is cleared. Table 8.3 shows activation source and

DTCER clearance. The activation source flag, in the case of RXI0, for example, is the RDRF flag

of SCI0.

Since there are multiple factors that can initiate DTC operation, the flag that initiated the transfer

is not cleared after the last byte (or word) is transferred. The corresponding interrupt handler must

perform the required processing.

Table 8.3

Activation Source and DTCER Clearance

Activation Source

When the DISEL Bit Is 0 and

the Specified Number of

Transfers Have Not Ended

When the DISEL Bit Is 1, or when

the Specified Number of Transfers

Have Ended

Software activation

The SWDTE bit is cleared to 0

The SWDTE bit remains set to 1

An interrupt is issued to the CPU

Interrupt activation

The corresponding DTCER bit

remains set to 1

The activation source flag is

cleared to 0

The corresponding DTCER bit is cleared

to 0

The activation source flag remains set to 1

A request is issued to the CPU for the

activation source interrupt

Figure 8.3 shows a block diagram of activation source control. For details see section 5, Interrupt

Controller.

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