H8SSLASH2214 datasheet(327/936 Pages) RENESAS

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Section 8 Data Transfer Controller (DTC)

Rev.4.00 Sep. 18, 2008 Page 267 of 872

REJ09B0189-0400

Interrupt Source

Origin of

Interrupt

Source

Vector

Number

Vector

Address

DTCE*

Priority

DEND0A (channel 0/channel 0A

transfer end)

DMAC

H'0490

DTCEE7

High

DEND0B (channel 0B transfer end)

H'0492

DTCEE6

DEND1A (channel 1/channel 1A

transfer end)

H'0494

DTCEE5

DEND1B (channel 1B transfer end)

H'0496

DTCEE4

RXI0 (reception complete 0)

H'04A2

DTCEE3

TXI0 (transmit data empty 0)

SCI

channel 0

H'04A4

DTCEE2

RXI1 (reception complete 1)

H'04AA

DTCEE1

TXI1 (transmit data empty 1)

SCI

channel 1

H'04AC

DTCEE0

RXI2 (reception complete 2)

H'04B2

DTCEF7

TXI2 (transmit data empty 2)

SCI

channel 2

H'04B4

DTCEF6

EXIRQ0

104

H'04D0

DTCEG7

EXIRQ1

105

H'04D2

DTCEG6

EXIRQ2

106

H'04D4

DTCEG5

EXIRQ3

107

H'04D6

DTCEG4

EXIRQ4

108

H'04D8

DTCEG3

EXIRQ5

109

H'04DA

DTCEG2

EXIRQ6

110

H'04DC

DTCEG1

EXIRQ7

External

module

111

H'04DE

DTCEG0

Low

Note: * DTCE bits with no corresponding interrupt are reserved, and should be written with 0.

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