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MCIMX503CVM8B 数据表(PDF) 61 Page - Freescale Semiconductor, Inc |
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MCIMX503CVM8B 数据表(HTML) 61 Page - Freescale Semiconductor, Inc |
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61 / 134 page  Electrical Characteristics i.MX50 Applications Processors for Consumer Products, Rev. 2 Freescale Semiconductor 61 Table 42. EIM Bus Timing Parameters 1 1 t is axi_clk cycle time. The maximum allowed axi_clk frequency is 133 MHz, whereas the maximum allowed EIM_BCLK frequency is 66.5 MHz. As a result, if BCD = 0, axi_clk must be ≤ 66.5 MHz. If BCD = 1, then 133 MHz is allowed for axi_clk, resulting in a EIM_BCLK of 66.5 MHz. When the clock branch to EIM is decreased to 66.5 MHz, other buses are impacted which are clocked from this source. See the CCM chapter of the MCIMX50 Applications Processor Reference Manual (MCIMX50RM) for a detailed clock tree description. ID Parameter BCD = 0 BCD = 1 BCD = 2 BCD = 3 Min Max Min Max Min Max Min Max WE1 EIM_BCLK Cycle time2 t— 2t — 3t — 4t — WE2 EIM_BCLK Low Level Width 0.4t — 0.8t — 1.2t — 1.6t — WE3 EIM_BCLK High Level Width 0.4t — 0.8t — 1.2t — 1.6t — WE4 Clock rise to address valid3 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75 WE5 Clock rise to address invalid 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75 WE6 Clock rise to EIM_CSx valid 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75 WE7 Clock rise to EIM_CSx invalid 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75 WE8 Clock rise to EIM_RW valid 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75 WE9 Clock rise to EIM_RW invalid 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75 WE10 Clock rise to EIM_OE valid 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75 WE11 Clock rise to EIM_OE invalid 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75 WE12 Clock rise to EIM_EBx valid 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75 WE13 Clock rise to EIM_EBx invalid 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75 WE14 Clock rise to EIM_LBA valid 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75 WE15 Clock rise to EIM_LBA invalid 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 3t – 1.25 3t + 1.75 WE16 Clock rise to Output Data valid 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 2t – 1.25 2t + 1.75 WE17 Clock rise to Output Data Invalid 0.5t – 1.25 0.5t + 1.75 t – 1.25 t + 1.75 2t – 1.25 2t + 1.75 2t – 1.25 2t + 1.75 WE18 Input Data setup time to Clock rise 2 — 2 — 2— 2— WE19 Input Data hold time from Clock rise 2.5 — 2.5 — 2.5 — 2.5 — WE20 EIM_WAIT setup time to Clock rise 2 — 2 — 2— 2— WE21 EIM_WAIT hold time from Clock rise 2.5 — 2.5 — 2.5 — 2.5 — |
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