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MCIMX503CVM8B 数据表(PDF) 74 Page - Freescale Semiconductor, Inc |
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MCIMX503CVM8B 数据表(HTML) 74 Page - Freescale Semiconductor, Inc |
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74 / 134 page  i.MX50 Applications Processors for Consumer Products, Rev. 2 74 Freescale Semiconductor Electrical Characteristics 4.9.2.2 CSPI Slave Mode Timing Figure 33 depicts the timing of CSPI in slave mode. Table 50 lists the CSPI slave mode timing characteristics. Figure 33. CSPI Slave Mode Timing Diagram Table 50. CSPI Slave Mode Timing Parameters ID Parameter Symbol Min Max Unit CS1 CSPIx_CLK Cycle Time tclk 60 — ns CS2 CSPIx_CLK High or Low Time tSW 15 — ns CS3 CSPIx_CLK Rise or Fall tRISE/FALL —— ns CS4 CSPIx_CS_x pulse width tCSLH 30 — ns CS5 CSPIx_CS_x Lead Time (CS setup time) tSCS 5— ns CS6 CSPIx_CS_x Lag Time (CS hold time) tHCS 5— ns CS7 CSPIx_DO Setup Time tSmosi 5— ns CS8 CSPIx_DO Hold Time tHmosi 5— ns CS9 CSPIx_DI Setup Time tSmiso 5— ns CS10 CSPIx_DI Hold Time tHmiso 5— ns CS1 CS7 CS8 CS2 CS2 CS4 CS6 CS5 CS9 CS10 CSPIx_CLK CSPIx_CS_x CSPIx_DI CSPIx_DO CS3 CS3 |
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