MCIMX503CVM8B datasheet(18/134 Pages) FREESCALE

18 / 134 page

i.MX50 Applications Processors for Consumer Products, Rev. 2

Freescale Semiconductor

Modules List

DRAM_OPEN,

DRAM_OPENFB (for 416

MAPBGA and 400 MAPBGA)

These pins are the echo gating output and feedback pins used by the DRAM PHY to bound a

window around the DQS transition. For an application using a single DRAM device, these pins

should be routed so that the

trace length (DRAM_OPEN + DRAM_OPENFB) =

trace length (DRAM_SDCLK0 + DRAM_SDQS0).

For an application using two DRAM devices, they should be routed so that the

trace length (DRAM_OPEN + DRAM_OPENFB) =

trace length (AVG(DRAM_SDCLK0+DRAM_SDCLK1) + AVG (DRAM_SDQS0_to_Device0 +

DRAM_SDQS0_to_Device1)).

This connection is required for LPDDR1, LPDDR2, and DDR2. For the i.MX50 PoP package,

these signals are connected on the substrate.

DRAM_SDODT0 (for 416

MAPBGA and 400 MAPBGA),

DRAM_SDODT1 (for 416

MAPBGA only)

These pins are the On-die termination outputs from the i.MX50.

For DDR2, these pins should be connected to the DDR2 DRAM ODT pins. For LPDDR1 and

LPDDR2, these pins should be left floating. Note that both SDODT pins are removed on the

416 PoPBGA package, and only SDODT0 exists on the 400 MAPBGA package.

DRAM_CALIBRATION

This pin is the ZQ calibration used to calibrate DRAM Ron and ODT.

For LPDDR2, this pin should be connected to ground through a 240

Ω 1% resistor. For DDR2

and LPDDR1, this pin should be connected to ground through a 300

Ω 1% resistor.

JTAG_MOD

This input has an internal 100K pull-up, by default. Note that JTAG_MOD is referenced as

SJC_MOD in the

MCIMX50 Applications Processor Reference Manual (MCIMX50RM) - both

names refer to the same signal. JTAG_MOD must be externally connected to GND for normal

operation. Termination to GND through an external pull-down resistor (such as 1 k

Ω) is

allowed. If JTAG port is not needed, the internal pull-up can be disabled in order to reduce

supply current to the pin.

JTAG_TCK

This input has an internal 100K pull-down. This pin is in the NVCC_JTAG domain.

JTAG_TDI

This input has an internal 47K pull-up to NVCC_JTAG. This pin is in the NVCC_JTAG domain.

JTAG_TDO

This is a 3-state output with an internal gate keeper enable to prevent a floating condition. An

external pull-up or pull-down resistor on JTAG_TDO is detrimental and should be avoided. This

pin is in the NVCC_JTAG domain.

JTAG_TMS

This input has an internal 47K pull-up to NVCC_JTAG. This pin is in the NVCC_JTAG domain.

JTAG_TRSTB

This input has an internal 47K pull-up to NVCC_JTAG. This pin is in the NVCC_JTAG domain.

These signals are No Connect (NC) and should be floated by the user.

LOW_BATT_GPIO

If the LOW_BATT_GPIO (UART4_TXD) is asserted at power up, the i.MX50 will boot up at a

lower ARM clock frequency to reduce system power. The actual ARM clock frequency used

when LOW_BATT_GPIO is asserted is determined by the BT_LPB_FREQ[1:0] pins (220 MHz

to 55.3 MHz). The polarity of the LOW_BATT_GPIO is active high by default, but may be set

to active low by setting the LOW_BATT_GPIO_LEVEL OTP bit.

See the “System Boot” chapter of the Reference Manual for more details.

Note that this is not a dedicated pin: LOW_BATT_GPIO appears on the UART4_TXD pin.

PMIC_STBY_REQ

This output may be driven high when the i.MX50 enters the STOP mode to notify the PMIC to

enter its low power standby state. This output is in the NVCC_SRTC domain.

PMIC_ON_REQ

This output from the i.MX50 can instruct the PMIC to turn on when the i.MX50 only has

NVCC_SRTC power. This may be useful for an alarm application, as it allows the i.MX50 to

turn off all blocks except for the RTC and then power on again at a specified time. This output

is in the NVCC_SRTC domain.

Table 5. Special Signal Considerations (continued)

Signal Name

Remarks

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